Digital-to-analog converters (DACs) convert a digital input into an analog signal. Capacitive DACs (CDACs) perform this task capacitively using a binary-weighted capacitor array. The capacitor array includes a number of capacitors ranging from the largest, responsible for converting the most significant bit (MSB) of data, to the smallest, responsible for converting the least significant bit (LSB) of data. Each capacitor is a separate leg of the array, where the total number of legs is determined by the number of bits in the digital input. Typically, the number of bits of the digital input is determined by the system resolution requirements. For higher-accuracy systems, a larger number of leas are required for the CDAC, leading to a larger capacitor array. Thus, CDACs can have large area requirements, provide increased loading on any connected circuitry, and exhibit increased dynamic power consumption from driving the individual legs. Given that most CDACs are differential in practical applications, these requirements are multiplied by a factor of two. Accordingly, it is desirable to provide a CDAC that satisfies the system resolution requirements, while requiring less implementation area, providing less loading on connected circuitry, and exhibiting less dynamic power consumption.